In the semiconductor industry, so-called “flip-chips,” as well as semiconductor dice of other configurations, may be attached to a substrate, such as a printed circuit board (PCB), interposer, or another semiconductor die, through an array of conductive elements comprising bumps, studs, columns or pillars. A dielectric underfill material may fill a gap between the semiconductor die and the substrate. FIG. 1 through 4 illustrate a conventional so-called “wafer level underfill” (WLU) method of attaching a semiconductor die 11 to a substrate 40. As shown in FIG. 1, an array of conductive elements 12 is formed on a surface of a semiconductor wafer 10 including multiple semiconductor dice 11. After the conductive elements 12 are formed on the semiconductor wafer 10, a dielectric WLU material 30 is deposited on the surface of the semiconductor wafer 10, as shown in FIG. 2. The WLU material 30 may be spin coated if in flowable form or laminated if in film form on the surface of the semiconductor wafer 10 with the array of conductive elements 12 formed thereon. The WLU material 30 at least partially covers the conductive elements 12 of the array.
Referring to FIG. 3, after the WLU material 30 is deposited over the semiconductor wafer 10, including at least partially over the conductive elements 12, the semiconductor wafer 10 is diced into individual semiconductor dice 11. Each semiconductor die 11 includes conductive elements 12 and WLU material 30 on a major surface thereof. Referring to FIG. 4, each semiconductor die 11 is positioned over a substrate 40, with the conductive elements 12 aligned with bond pads 42 of the substrate 40, and attached to the substrate 40 through a thermal compression process. The WLU material 30 melts and flows to fill the gap between the semiconductor die 11 and the substrate 40, and the WLU material 30 solidifies, which may involve curing, depending on the material of the WLU.
Ideally, the melted WLU material 30 flows off of each conductive element 12 during the bonding operation to enable an electrical interconnection to be made between the conductive elements 12 and the bond pads 42. However, a portion of the WLU material 30 often does not flow off of at least some of the conductive elements 12 and becomes entrapped between the conductive elements 12 and their associated bond pads 42. The entrapped WLU material 30 may increase electrical resistance across the electrical interconnection or cause the electrical interconnection to fail. Even a small amount of entrapped WLU material 30 may result in weakened joint integrity, which may result in early failure. Such defects may lower the performance of a device including the semiconductor die 11 and the substrate 40, or may even render the entire device inoperable. However, the WLU method enables application of underfill material to the entire semiconductor wafer 10, which saves time and cost of manufacturing when compared to methods that provide underfill material in a gap under individual semiconductor dice.
FIG. 5 through 7 illustrate a so-called “capillary underfill” (CUF) method of attaching the semiconductor die 11 to the substrate 40. In the conventional CUF method, the semiconductor die 11 is positioned over the substrate 40 such that the conductive elements 12 are aligned with the bond pads 42 of the substrate 40, as shown in FIG. 5. Referring to FIG. 6, the conductive elements 12 are placed in contact with the bond pads 42 and the semiconductor die 11 is thermally compressed against the substrate 40. Through the thermal compression, solder on the tips of the conductive elements 12 may melt to wet the bond pads 42 and form a physical and electrical interconnection. As shown in FIG. 7, after the solder is cooled and hardened, a relatively low-viscosity, liquid dielectric CUF material 32 is introduced into a gap between the semiconductor die 11 and the substrate 40 along one or more edges of the gap and is allowed to fill in the gap by wetting of surfaces and capillary action. The CUF material 32 flows between and around the conductive elements 12 and the bond pads 42, and the CUF material 32 is subsequently cured and hardened. The CUF method enables the electrical connections between the conductive elements 12 and the bond pads 42 to be free of entrapped underfill material, which improves the electrical connections and performance thereof. However, providing the CUF material 32 in the gaps under individual semiconductor dice 11 increases the time and cost of manufacturing compared to the WLU method. Furthermore, as semiconductor dice 11 and their respective conductive elements 12 are reduced in size, according to the well-known trend in the semiconductor industry toward smaller sizes, it becomes increasingly difficult to fill in the gap between the semiconductor dice 11 and the substrates 40 without voids. When present, voids in the CUF material 32 may decrease the reliability, performance, and physical stability of devices formed with the semiconductor dice 11 and associated substrates 40.
FIGS. 8 and 9 illustrate a so-called “non-conductive paste” (NCP) method of attaching the semiconductor die 11 to the substrate 40. In the conventional NCP method, the substrate 40 and the bond pads 42 thereon are at least partially covered by a dielectric NCP underfill material 34 and the conductive elements 12 on the semiconductor die 11 are aligned with the bond pads 42, as shown in FIG. 8. Referring to FIG. 9, the conductive elements 12 are thermally compressed against the bond pads 42 to melt the solder of the conductive elements 12 and to form an electrical interconnection. Similar to the WLU method described above, the NCP underfill material 34 ideally flows away from the interface between the conductive elements 12 and the associated bond pads 42. However, as shown in FIG. 9, at least some of the electrical interconnections may include entrapped NCP underfill material 36 between the conductive elements 12 and the bond pads 42. The high viscosity nature and presence of filler material in NCP increase the likelihood that NCP material will become entrapped. As discussed above, such entrapped NCP underfill material 36 may increase electrical resistance across the electrical interconnection, cause the electrical interconnection to fail, weaken joint integrity, and/or cause early failure. Such defects may lower the performance of a device including the semiconductor die 11 and the substrate 40, or may even render the entire device inoperable.
If any of the conventional methods described above are used with semiconductor dice 11 having so-called “thin substrates” (e.g., less than about 100 μm), the underfill material may have an increased likelihood of contaminating the back side of the semiconductor die 11. For example, during bonding, the underfill material may flow out of the gap and along a peripheral edge of the semiconductor die 11 and ultimately to the back side (e.g., the side of the semiconductor die 11 opposite the substrate 40) of the semiconductor die 11. With semiconductor dice 11 having a thin substrate, the vertical distance that the underfill material must travel to reach the back side is substantially shortened. Therefore, there is a smaller margin of error in determining the amount of underfill material required to fill the gap without allowing excess underfill material to reach the back side of the semiconductor die 11, consequently increasing the likelihood of the back side being contaminated by the underfill material.